ASIC Physical Design Lead
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Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 10 years experience in ASIC physical design and methodologies in advanced process nodes.
- Experience leading teams through RTL to GDS physical design processes with knowledge of each phase.
- Experience driving place and route on complex designs using industry standard EDA CAD tools, including command execution, debugging, and custom technique development via Tcl or GUI.
- Experience with EMIR parameters and analysis techniques (eg., mitigating EMIR violations and making design tradeoffs related to power grid design and augmentation).
Preferred qualifications:
- Master's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- Experience with IO pads, RDL route, bump mapping, and boundary scan.
- Experience with physical IP integration (e.g. memories, IO's, analog PHYs).
- Experience with silicon interposer design.
- Experience crafting physical design automation flows.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an Application-Specific Integrated Circuit (ASIC) Physical Design Lead on the chip implementation team, you will work on the physical implementation of ASICs in advanced technology nodes. You will drive teams towards common execution goals by setting priorities and creating detailed task and check lists, tracking execution progress and status, course correcting as needed, escalating and resolving critical issues. You will be ultimately responsible to deliver physical designs at the floor plan block level, subsystem level, and chip level on schedule and to required quality levels. You will work on and lead teams performing physical design including place and route, EMIR, static timing, and physical verification. You will go beyond automated flow execution and use industry standard Exploratory Data Analysis (EDA) and Confirmatory Data Analysis (CDA) tools to perform custom design work, and to provide customized solutions to specific problems, and to enhance Power Performance Area (PPA).
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Drive the physical implementation of complex ASICs in advanced technology nodes at floor plan block, subsystem, and chip levels.
- Perform and lead teams in the execution of place and route using EDA and CAD tools, including command execution, debugging, and custom technique development via Tcl scripting and GUI interaction.
- Conduct in-depth EMIR analysis, identify and mitigate violations, and make informed tradeoffs related to power grid design and augmentation.
- Perform detailed Design Rule Check (DRC) analysis on base and metal layers in advanced process nodes, and resolve complex design violations.
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