Senior DFT Static Timing Analysis Engineer, Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in static timing (i.e., full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing margins).
- Experience in DFT architectures and associated test methodologies.
- Experience in Tessent generated DFT timing constraints, SSN bus networks and constraints and mode merging.
- Experience with EDA tools and EDA Tcl commands for timing analysis, timing closure, parasitic extraction, noise glitch, crosstalk.
- Experience with test mode timing constraint development.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience in STA, and in leading test mode timing constraint development and timing convergence for SOC projects.
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs and shipping silicon.
- Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
- Experience in planning the clock distribution architecture for critical test modes.
- Knowledge of semiconductor device physics and SPICE simulation and full-chip static timing topics.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will work on the physical implementation of Application-specific integrated circuits (ASIC) using advanced technology nodes. You will work on timing constraint development and validation for test and functional modes, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. You will perform technical evaluations of vendors, tools, methodologies, and will provide recommendations. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to understand and implement their requirements.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Own test mode timing constraint creation and validation, perform timing analysis and timing Engineering Change Order (ECO) creation, and oversee final timing sign-off for complex ASICs.
- Collaborate with the DFT team and optimize DFT architecture and also timing constraints to ensure successful timing closure.
- Participate in both static timing analysis methodology development and support, as well as chip implementation and timing signoff execution.
- Develop, support and execute implementation flows around industry-standard static timing and parasitic extraction tools.
- Debug flow issues reported by the team, and work with EDA vendors to resolve them where necessary.
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