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ASIC DFT Engineer, Silicon

GoogleBengaluru, Karnataka, India

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  • 3 years of experience with SoC-level design for test (DFT) architecture, implementation, and validation.
  • Experience with SoC DFT RTL implementation, RTL verification, ATPG/ MBIST/BSCAN/IDDQ pattern generation.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  • Experience with silicon process and technology nodes for high speed and low power consumption.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will drive the SoC-level design for test (DFT ) architecture, implementation, and validation. Your role combines high-level architectural planning with automation, SoC DFT RTL implementation, RTL verification, automatic test pattern generation (ATPG)/memory built-in self-test (MBIST)/boundary scan (BSCAN)/current drain-to-drain quiescent (IDDQ) pattern generation, validation and ATE production support, directly impacting the reliability and scalability of Google’s custom hardware.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

  • Develop test patterns that optimally tests the logic/memory/analog macro under test.
  • Work with internal cross-functional teams, external silicon partners, Product Engineering team, and intellectual property (IP) vendors to support structural validate and parametrically characterize the Silicon.
  • Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
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