Silicon Networking RTL Design Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).
- Experience in micro-architecture and design of Internet Protocols (IPs) and Subsystems.
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Preferred qualifications:
- Experience in Networking domain like Packet processing, bandwidth management, congestion control, etc.
- Experience with scripting languages (e.g., Python or Perl).
- Knowledge of bus architectures, fabrics, processor design, or memory hierarchies.
- Knowledge of high performance and low power design techniques.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Responsibilities
- Own Register-Transfer Level (RTL) implementation of Internet Protocols (IPs) and subsystems in Networking domain.
- Work with design team members to close feature definitions and develop micro-architecture specifications.
- Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
- Work on Power, Performance and Area improvements for the domains owned.
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