Software Engineer, TPU Compiler Development Infrastructure
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Minimum qualifications:
- Bachelor’s degree or equivalent practical experience.
- 2 years of experience with coding in C++ and Python, or 1 year of experience with an advanced degree.
- 2 years of experience working with Google Infrastructure such as Blaze, TAP, or Guitar.
Preferred qualifications:
- Master's degree or PhD in Computer Science, or a related technical field.
- Interest in becoming an expert in infrastructure surrounding low-level ML hardware programming.
About the job
Our team develops the Accelerated Linear Algebra (XLA) compiler which enables TPUs, Google's in-house custom designed processor, to accelerate machine learning and other scientific computing workloads for both internal Google customers and external Cloud customers.
The XLA TPU team is reaching a critical threshold of complexity at a time when the demand for rapid iteration has never been higher. This role is designed to manage the infrastructure friction that compiler engineers face daily, effectively multiplying output of the entire team.
In concrete terms we need to pull down the average team presubmit latency from the current 1.5. hours to 20 min and minimize Changelist (CL) rollback (catch issues early).
While this position does not require prior experience with compilers, hardware, or deep ML expertise, bout it does require someone who genuinely enjoys the craft of building great infrastructure unblocking developer productivity.
Responsibilities
- Reduce CL time to submit for a CL and minimize CL rollback for the whole XLA TPU team. Drive infrastructure improvements that remove friction from the daily development of the XLA TPU Compiler team.
- Develop tools supporting compiler engineers as they work through stages of new TPU introduction (e.g., testing when hardware is not yet available or very limited).
- Modernize and simplify build/test fixtures (e.g. xla_test) to make them more reliable and easier for the team to use.
- Design and implement system architectures which cleanly handle ever increasing number of TPU generations and compiler features, ensuring the codebase doesn't become a "spaghetti" of special cases.
- Identify and resolve accelerator utilization bottlenecks, improve accelerator test coverage without slowing down CL submission.
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