Design Verification Engineer, Silicon Engineering
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience in verifying digital logic at Register Transfer Logic level using SystemVerilog and Formal Verification Techniques.
- Experience with verification techniques, System Verilog Assertions, and assertion-based verification.
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Science.
- Experience creating and using verification components and environments in a standard verification methodology such as UVM.
- Experience with Interconnect Protocols (e.g., AXI, ACE, CHI, CCIX, CXL).
- Architectural background in one or more of: Memory Management, Caches Hierarchies, Coherency, DDR/LPDDR, PCIe, or Packet Processors.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan and execute the verification of the next generation configurable interconnect, memory management, power controller, and chips pervasive IP.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
- Develop cross-language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases and debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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