Senior Staff, Mixed-Signal and High Speed IO Design, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
- 15 years of experience in analog mixed signal or high-speed IO development.
- Experience defining mixed-signal or high-speed I/O designs and taking them to high-volume manufacturing HVM.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on wireline silicon architecture and design.
- Experience with technical innovation in mixed-signal and high-speed IO solutions.
- Experience working on high-performance, data-center class IP, from concept through deployment.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will shape the future of Data Center silicon. Powering Google's most demanding Compute and AI/ML applications, our portfolio spans CPU, TPU, Networking, and other key data center technologies. As part of a nascent team pushing boundaries and developing advanced custom IP, you will bring expertise in one or more of the following areas: wireline communications, analog circuit design, DSP design and algorithms, signal integrity, transmission line theory, advanced analog and mixed-signal modeling, clocking, CDR, equalization, or high-speed I/O industry standards. You will collaborate across cross-functional organizations to deliver designs for Google’s advanced data center products, bringing out the best in your team to achieve mission-critical results.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Design high-speed analog/digital circuits (e.g., ADC, DAC, PLL, CDR, DSP), optimizing for Power, Performance, and Area (PPA).
- Model and simulate channel behavior (S-parameters), signal integrity, and jitter using tools like MATLAB.
- Bring up new silicon, characterizing performance and testing for electrical compliance in lab environments.
- Collaborate with packaging, board design, and firmware teams to ensure seamless integration into System-on-Chips (SoCs).
- Adhere to industry standards (e.g., IEEE or OIF) for high-speed protocols to optimize performance and power consumption.
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