Design for Testability Engineer Lead, Silicon
- linkCopy link
- emailEmail a friend
Minimum qualifications:
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
- 8 years of experience in DFT/DFD flows and methodologies.
- Experience with DFT EDA Tool Tessent/Genus/FC/Simvision, etc.
- Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.
Preferred qualifications:
- Experience with industry DFT, MBIST, and ATPG tools.
- Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG.
- Understanding of the end to end flows (e.g., design, verification, DFT and PD phases in a SOC cycle).
- Proficiency with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool.
- Proficiency with a scripting language such as Perl or Python.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Collaborate with a team of DFT engineers, working closely with RTL, Physical Design, SoC DFT, and Product Engineering teams.
- Architect SoC and Subsystem Memory Built-In Self-Test (MBIST) structures across multiple voltage and power domains.
- Drive cross-functional design efforts regarding memory repair methodology and system-level integration.
- Own Gate-Level Simulation (GLS) verification and debug sign-off, ensuring total functional and timing coverage.
- Develop MBIST TbGen, pattern generation, and DFT simulation flows, including scripting to automate and optimize the DFT environment.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.