Senior Silicon Bring Up and Test Manager, Raxium
- linkCopy link
- emailEmail a friend
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in ASIC or SoC design, including test, and custom chip development with Design-for-Test (DFT) implementation.
- Experience working with vendors and managing development schedule and specifications.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with EDA tools for synthesis, Static Timing Analysis (STA), DFT, and test tool conversion.
- Experience with DFT techniques such as hierarchical DFT, compression, and diagnosis.
- Experience in display back plane panel technology.
- Experience in hardware description languages (e.g., Verilog, SystemVerilog).
- Excellent problem-solving and communication skills.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.Responsibilities
- Plan daily activities and provide technical direction for test operations in Taiwan. Partner with design houses to maintain and improve test programs and functional sequences.
- Manage relationships with software vendors to catalog test results, maps, and related data.
- Drive validation flow improvements using new tools and scripts to improve test efficiency and coverage.
- Collaborate with the documentation team to validate specifications, margins, and acceptance criteria.
- Work with verification teams on test plans and logic debugging. Assist in root-cause analysis of silicon failures with design and test engineering teams.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.