Design AI Lead, Google Cloud
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 15 years of experience in design from microarchitecture through implementation using Verilog/SystemVerilog.
- 10 years of experience in managing teams and groups.
- Experience working with system design principles for low latency, high throughput, security, and reliability.
- Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
- Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
- Master's degree or PhD in Engineering or equivalent practical experience.
- Experience in micro-architecture and design of complex AI modules, optimizing their power, performance and area.
- Experience in leading chip development projects and teams, and execution.
- Ability to motivate and focus on collaborative teams to achieve testing goals.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead an edge AI IP design team including definition, implementation and deployment and define IP development methodologies sharing unified blocks within the IP design team.
- Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
- Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
- Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
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