ASIC Design Verification Engineer, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 2 years of experience in verifying digital logic at RTL using System Verilog for FPGAs and ASICs.
- Experience with UVM Tesbenches or environments.
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Science with 6 years of relevant experience or a Bachelor’s degree with 8 years of experience.
- Experience with Advanced Microcontroller Bus Architecture (AMBA) (e.g., Android Play Books (APB), Advanced eXtensible Interface (AXI), App Campaigns for Engagement (ACE) or other standard protocols.
- Expertise in creating/using verification components and environments in UVM methodology at IP or Subsystem level.
- Experience with image processing, computer vision or machine learning IPs.
- Familiarity with CPU, GPU or other computer architectures.
About the job
The team designs and builds the hardware, software and networking technologies that power all of Google's services.
As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most effective computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. You will shape the machinery that goes into data centers affecting millions of Google users.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
- Create and improve constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Optionally use Stored Value Account (SVA) and formal tools for formal verification.
- Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and Dynamic Voltage and Frequency Scaling (DVFS). Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
- Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.
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