Senior ASIC Performance and Power Architect, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of experience in SoC performance or power analysis, modeling and optimizations.
- Experience with SoC architectures and performance and power KPIs.
Preferred qualifications:
- Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
- Experience with use case datapaths, 2-3 IP-level and SoC-level performance KPIs and power management concepts.
- Experience of team lead and technical lead.
- Experience with Python.
- Knowledge of the impact of software and architectural design decisions on system power and thermal behavior.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Define and drive low power solutions for Google SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
- Create use case workload and data flow models for DoU (day of use) power evaluation and drive power and performance optimizations through SoC generations.
- Define performance/power Key performance indicators (KPIs) and SoC/IP-level performance/power targets, guide architecture and design to achieve lower power targets to perform power roll ups and track power throughout the design cycle.
- Propose and drive power optimizations throughout the design process from concept to mass productization.
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
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