Design Engineer, Custom Circuits, Static Random Access Memory
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).
- Experience with custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
- Experience in scripting and automation using Tcl and Python (or Perl).
- Experience with SPICE and transistor level design in advanced nodes.
- Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience working with major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.
- Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
- Understanding of collaterals for front end and back end design teams.
- Excellent track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout.
About the job
As a Design Engineer, Custom Circuits and Static Random-Access Memorys (SRAMs) you will collaborate with circuit design, SRAM, physical design, technology, and architecture leads to deliver cutting-edge ASIC’s and SoC’s. You will work on topics that span circuit design, memories, digital block optimization, clock distribution, floorplanning, third-party IPs, and foundry engagement. You will be responsible for managing the product Power Performance Area (PPA) by developing, optimizing, and integrating advanced SRAMs and other circuits.
In this role you will conduct evaluations of custom SRAMs and drive selection of the optimal configurations and design architectures/features with foundry and vendor partner teams. You will supervise execution and deployment of the memories from inception to project integration and to tapeout. You will further evaluate foundry process node PPA entitlement, identify product PPA bottlenecks, and drive new and novel circuit initiatives.
By co-optimizing across the entire design space, you will participate in the development of exceptional technology in high-performance computing and define the next generation of datacenter-class silicon. By navigating the trade-offs in SRAMs and other critical circuits, you will ensure Google’s hardware achieves efficiency and power density.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Responsibilities
- Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits. Drive proper IP integration and margins with the physical design team.
- Partner with foundries and IP providers, as well as internal technology, physical design, and architecture teams, to optimize products for PPA, schedule, and reliability in advanced CMOS nodes.
- Drive and support test chip design, execution, and validation of critical circuit IPs.
- Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
- Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
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