Performance Architect, Use Case and Workload Analysis
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience in embedded system software development, test and debugging.
- Experience in programming (e.g., Python, or C/C++, Shell script).
- Experience with Android/Linux environments.
Preferred qualifications:
- Experience in silicon characterization, system-level test (SLT), chip bring-up, hardware debugging, and failure analysis (FA).
- Expertise in performance and power analysis for CPUs, GPUs, TPUs, interconnect fabrics, and memory systems, including QoS tuning and bandwidth/latency analysis.
- Knowledge of OS kernel-level optimization, including schedulers, DVFS/idle governors, thermal management, and device drivers.
- Understanding of Dynamic Voltage and Frequency Scaling (DVFS) control, thermal frameworks, power state control, and Power Management ICs (PMICs).
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Responsibilities
- Conduct CPU power and performance correlation.
- Conduct CPU workload analysis and optimization on real use cases and commercial benchmarks.
- Drive post-silicon characterization and failure analysis for next-generation CPU and memory systems, focusing on optimizing F_max/V_min boundaries and root-causing complex silicon-level bugs.
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