Full Chip CAD Physical Design Verification Engineer
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field.
- Experience in Electronic Design Automation (EDA) tools and RTL2GDS flows.
- Experience in the semiconductor/EDA industry.
Preferred qualifications:
- Master’s degree in Computer Engineering/EE.
- Experience related to silicon quality or reliability.
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Demonstrate an understanding of the Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow, with experience in using Cadence design tools.
- Be involved in implementing large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, demonstrate an understanding of associated issues and solutions.
- Possess floorplanning, power grid design, and place-and-route methodologies, with expertise in using Synopsis tools like Floorplan Compiler (FC) and formality.
- Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
- Possess scripting skills in Synopsis TCL, with expertise in Python.
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