RTL Design Engineer, Security, Silicon
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Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 3 years of experience designing Register Transfer Level (RTL) digital reasoning using SystemVerilog for Field-programmable Gate Array (FPGA)/Application-specific integrated circuits (ASICs).
- Experience with Application-specific integrated circuits (ASIC) design methodologies and QA flows (e.g., VCLP, Lint, CDC, RDC, SGDFT).
- Experience with a scripting language such as Perl or Python.
- Experience in area, power and performance optimization.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on Computer Architecture, or a related field.
- Experience with Unified Power Format (UPF) and VCLP.
- Experience in design and development of security blocks or crypto blocks.
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Perform Verilog/SystemVerilog Register Transfer Level (RTL) coding, functional or performance simulation debug.
- Participate in test planning and coverage analysis.
- Develop Register Transfer Level (RTL) implementations that meet power, performance and area goals.
- Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up.
- Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in Architecture, Register Transfer Level (RTL) design, verification, Design for testing (DFT) and Partner Domains (PD).
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