Circuit Design Engineer, University Graduate
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience with VLSI design coursework or internships involving transistor-level circuit design.
- Experience in SPICE simulation (e.g., HSPICE, Spectre) and CMOS logic.
- Experience in circuit design.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with custom layout design and physical verification (e.g., DRC, LVS, ERC) through academic projects or internships.
- Experience with scripting and programming (e.g., Python, TCL, or Perl).
- Familiarity with physical design concepts (e.g., place and route, timing analysis).
- Ability to communicate technical concepts clearly and effectively in a collaborative, team-oriented environment.
- Strong problem-solving skills, with the ability to distill complex simulation data into actionable summaries.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Circuit Design Engineer, you will join a group of engineers dedicated to pushing the physical limits of semiconductor technology. In this role, you will bridge the gap between academic theory and industry-leading silicon by working on the fundamental building blocks of Google’s Tensor Processing Units (TPUs).
You will gain experience in the design and optimization of standard cell libraries, exploring the intricate trade-offs between power, performance, and area (PPA) at the transistor level. Working within our technology team, you will assist in evaluating advanced process nodes and collaborating with external foundry partners to refine our design kits and IPs.
You will have the opportunity to contribute to custom standard cell layouts and develop a deep understanding of how circuit-level decisions impact the scale of Google’s global AI infrastructure. This role is designed for a motivated engineer eager to master advanced CMOS nodes, SPICE simulation, and the physical design methodologies required to deliver the next generation of custom high-performance computing.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Support the design and customization of standard cells, performing transistor-level SPICE simulations to validate power and timing performance.
- Assist in layout development and verification (DRC/LVS) for custom library cells, ensuring compliance with advanced foundry design rules.
- Help evaluate Process Design Kit (PDK) releases by running benchmarking tests and analyzing PPA impacts on digital blocks.
- Collaborate with engineers to debug technical collaterals and document methodology improvements for our standard cell flows.
- Participate in cross-functional syncs with physical design and foundry teams to learn and implement Design-Technology Co-Optimization (DTCO) strategies.
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