CPU Digital Design Manager, Silicon
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 15 years of experience with leading design teams.
- Experience in one or more of the following sub-systems: CPU cores (e.g., ARM), GPU graphics processors, HSIO protocols (e.g., PCIe, UFS, LPDDR), or LSIO peripherals.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Proficiency with modern ASIC design methodologies and tools for front-end quality checks, including Lint, Clock/Reset Domain Crossing (CDC/RDC), Synthesis, and power-aware design using UPF.
- Understanding of the complete SoC design lifecycle and the interplay between front-end design, verification (DV), DFT, and physical design (PD).
About the job
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead, mentor, and manage a high-caliber team of ASIC RTL Engineers responsible for the integration and delivery of critical SoC sub-systems, including CPU, GPU, High-Speed IO (HSIO), and Low-Speed IO (LSIO).
- Provide technical leadership and ownership for these sub-systems, from microarchitecture definition through to tape-out and silicon bring-up.
- Drive project execution by planning tasks, setting priorities, holding code and design reviews, and overseeing the development of complex features and logic.
- Collaborate closely with SoC architects to interpret specifications and develop robust implementation strategies that meet stringent Power, Performance, and Area (PPA) goals for premium-tier mobile products.
- Serve as the primary design interface for cross-functional teams, including Verification, Physical Design, Design-for-Test (DFT), and Software/Firmware, to ensure seamless integration and resolve key technical challenges.
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